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Inter-Integrated Circuit
9.3.2.5
I 2 C Data I/O register
7
6
5
4
3
2
1
0
Read
DATA
Write
Reset
0
0
0
0
0
0
0
0
= Unimplemented or reserved
Figure 9-6. I 2 C Data I/O register (IICD)
Table 9-8. 2 C Data I/O register (IICD) field descriptions
Bit(s)
7–0
Field
DATA
Description
Data
In master transmit mode, when data is written to the IICD, a data transfer is initiated.
The most significant bit is sent first. In master receive mode, reading this register initiates receiving
of the next byte of data.
NOTE
When transitioning out of master receive mode, the I 2 C mode must be
switched before reading the IICD register to prevent an inadvertent
initiation of a master receive data transfer.
In slave mode, the same functions are available after an address match has occurred.
TX bit in IICC must correctly reflect the desired direction of transfer in master and slave modes for the
transmission to begin. For instance, if the I 2 C is configured for master transmit but a master receive is
desired, then reading the IICD does not initiate the receive.
Reading the IICD returns the last byte received while the I 2 C is configured in either master receive or slave
receive modes. The IICD does not reflect every byte that is transmitted on the I 2 C bus, nor can software
verify that a byte has been written to the IICD correctly by reading it back.
In master transmit mode, the first byte of data written to IICD following assertion of MST (start bit) or
assertion of RSTA bit (repeated start) is used for the address transfer and must comprise of the calling
address (in bit 7 to bit 1) concatenated with the required R/W bit (in position bit 0).
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
165
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